1. Technical Field
The present invention relates to bi-directional, simultaneous data buses, and more specifically, to glitch-free receivers for simultaneous, bi-directional data buses.
2. Related Art
Typically, on a bi-directional, simultaneous data bus, data is sent in both directions simultaneously. In a typical arrangement, for each physical transmission line of the bi-directional, simultaneous data bus, the output of a first driver and the input of a first receiver are electrically coupled to the first end of the transmission line, and the output of a second driver and the input of a second receiver are electrically coupled to the second end of the transmission line.
The first receiver interprets the digital signal being sent by the second driver from the second end to the first end of the transmission line by monitoring both the digital signal on the input of the first driver and the voltage level on the first end of the transmission line. Similarly, the second receiver interprets the digital signal being sent by the first driver from the first end to the second end of the transmission line by monitoring both the digital signal on the input of the second driver and the voltage level on the second end of the transmission line.
Assume that the inputs of the first and second drivers are initially at logic low and logic high, respectively (i.e., 0 and 1, respectively, in positive logic convention). Hereafter, positive logic convention is used. As a result, the first end of the transmission line is at ½Vcc (Vcc is the power supply voltage). Assume further that the input of the first driver switches from 0 to 1 while the input of the second driver is held at 1. In response, the first end of the transmission line is pulled from ½Vcc to Vcc. Hereafter, 0 and 1 represent logic statuses of digital signals, and analog voltage such as 0V, ground, Vcc, ½Vcc, etc., represent values of analog signals. Eventually, the first receiver will sense both the digital signal on the input of the first driver switching from 0 to 1 and the voltage level on the first end of the transmission line switching to Vcc. As a result, after the input of the first driver switches from 0 to 1, eventually, the first receiver will correctly interpret that a 1 is still being sent by the second driver from the second end to the first end of the transmission line. Accordingly, the first receiver generates a 1 at its output representing the logic value the second driver is sending from the second end to the first end of the transmission line.
However, there may be a time period during which the first receiver has sensed the digital signal on the input of the first driver switching from 0 to 1, but has not sensed the voltage level on the first end of the transmission line switching to from ½Vcc to Vcc. During this period, the first receiver incorrectly interprets that a 0 is being sent by the second driver from the second end to the first end of the transmission line. At the end of the time period, the first receiver senses the voltage level on the first end of the transmission line switching from ½Vcc to Vcc. Then, the first receiver will correctly interpret that a 1 is being sent by the second driver from the second end to the first end of the transmission line. In other words, there is a glitch during this time period.
As a result, a design of a receiver that is capable of eliminating glitches at its output is needed. A method is also needed for programming and operating the receiver so that glitches at its output are eliminated.